Sequencer-per-Pin Test System Architecture
Today there is a growing interest in DFT oriented testers, designed to make the application of automatically generated tests simple. This paper describes an ur-DFT tester, one designed to make the application of vectors from simulators easier. Though there were resource per pin testers before, this was the first with a sequencer per pin architecture, that could generate a complete set of events on each channel with full flexibility.
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