Defect Classes: An Overdue Paradigm for CMOS IC Testing
A multi-year research project was performed at and managed by Sandia National Laboratories to investigate and improve the understanding of the failure modes and logic effects of CMOS IC defects. This paper summarizes the results of this work by proposing a comprehensive strategy for testing using defect classes based on real defect electrical properties not abstract fault models. It stimulated subsequent work by others that expanded and improved the knowledge of the behavior of defects and the use of this type of information to improve CMOS IC testing. It paved the way for what is now known as defect-based testing.
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