Improved Boundary-Scan Design
The paper starts with a critique of the designs of boundary-scan cells in the IEEE 1149.1 Boundary-Scan Standard. The circuits shown in the Standard tend to dictate the actual implementation and, in so doing, carry penalties. For example, a classic BC_1 has an in-line multiplexer which adds delay to an output mission-mode signal or prevents input signal buffers from driving directly into the functional logic. In addition, a short between two or more outputs driven by boundary-scan cells (in EXTEST mode) may cause damage to unprotected output buffers. Whetsel's paper contains an alternative set of designs for standard boundary-scan cells that overcome the problems but that are still compliant to the requirements of 1149.1. He substitutes transistor switches for multiplexers and weak feedback buffers (latches) for output flip-flops. Such designs also provide other benefits, such a support for IDDQ test and tolerance to output shorts. Unfortunately, the designs were never used either by Texas Instruments (Whetsel's company) or by any EDA 1149.1-synthesis vendor. But, the designs are still fresh and applicable to situations where increase in silicon real estate, impact on performance or tolerance to shorts become real boundary-scan issues.
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