Weak-Write Test Mode: An SRAM Cell Stability Design-for-Test
Technique
Memory testing was a key aspect in the origins of ITC and there were many early papers about the challenges and benefits of various types of test methods for stand-alone SRAMs. The difficulties of thoroughly testing increasingly larger SRAMs were discussed, documented, and debated vigorously for many years, followed by a period of relatively little new work or progress. This paper provided a exciting new design for test technique, which has been adopted widely in some version or another. Its implementation is essentially as simple as other algorithmic tests and does not require extensive characterization. The improved detection of defective cells provided a valuable opportunity to increase test quality for stand-alone and embedded memories.
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