OPMISR: The Foundation for Compressed ATPG Vectors
Automatic test pattern generation (ATPG) for scan-based testing of complex CMOS ICs is one of the critical factors contributing to the market success of a wide variety of commercial products, including microprocessors, ASICs, and SOCs. It is a testament to the acceptance of practical design-for test (DFT) methodologies and is one of the enabling factors for the cost-effective testing of high volume commercial ICs with very restrictive time to market requirements. This paper addresses the need for reducing the ATPG data volume by the use of a scan architecture in conjunction with tester stored pattern stimulus data compression. It provided a large reduction in test data volume and greatly extended the useful life of existing ATE for those that implemented it.
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