Embedded Deterministic Test for Low-Cost Manufacturing Test
As ICs got larger, so did test vector counts. While ATE memories have kept up, test times increased, and the need for additional vectors for delay test, and possibly n-detect tests threatens to overwhelm us. Algorithmic test data compression techniques reached their practical limits almost a decade ago. While not the first work on hardware test compression, this paper, describing a practical implementation, revitalized the area, making compression a must-have feature of ATPG tools and increasing research in the area.
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